1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus and a driving method thereof, and more particularly to a photoelectric conversion apparatus in which sensor chips each including a plurality of photoreceiving elements are arranged and a driving method thereof.
2. Description of the Related Art
Conventionally, linear image sensors using photoelectric conversion apparatus are frequently used as reading apparatus of facsimile machines, scanners, and the like.
Since these linear image sensors are produced on silicon wafers, their sensor lengths are limited by their wafer sizes. Consequently, it is difficult to produce linear image sensor chips having the same lengths as those of originals, and only linear image sensor chips having shorter sensor lengths could be often obtained.
Accordingly, the reading apparatus have de-magnified the reflected lights from the originals with optical systems and conducts the de-magnified projection of the reflected lights onto the linear image sensors to read images.
However, the reading apparatus using such de-magnification optical systems have to take large spaces for the optical systems and cannot obtain sufficient resolution.
Accordingly, in order to resolve the problem, a multi-chip type image sensor including a plurality of linear image sensors arranged on a straight line has been used.
A configuration disclosed in Japanese Patent No. 2823578 has conventionally been known as a configuration of the multi-chip type image sensors.
In order to reduce manufacturing costs by increasing the number of chips produced from one silicon wafer as much as possible, efforts of reducing (hereinafter also expressed as shrinking) chip sizes have conventionally been performed.
As a method of shrinking chip sizes, the method in which of a plurality of photoreceiving elements share a scanning shift register, a capacitor element for temporarily storing electric signals generated in the photoreceiving elements, and the like, is generally known.
Because the method enables the reduction of the numbers of the elements and components, such as the shift registers and the capacitor elements, which have relatively larger occupation areas, the method enables the reduction of a chip size.
In case of an image sensor chip realized by the method, a plurality of photoreceiving elements shares a shift register and a capacitor element. Consequently, it is impossible to read out the electric signals generated in all of the photoreceiving elements by a single readout scanning.
In order to conduct the readout operations of all the photoreceiving elements, the readout operations of the electric signals generated in a part of the photoreceiving elements are first conducted in order by scanning a shift register.
Next, the readout operations of the electric signals generated by the photoreceiving elements the readout operations of which have not been performed in the preceding scanning are performed by scanning the shift register again.
By repeating the readout scanning mentioned above the times of the number of photoreceiving elements sharing the shift register and the capacitor element, the readout operations of all of the photoreceiving elements are completed.
However, in case of the readout method mentioned above, a time period for conducting the switching to other photoreceiving elements for the next readout scanning becomes a blanking time period during which no optical signals can be output. Consequently, the blanking time periods in an optical signal outputting period increase in proportion to the number of repetitions of the scanning.
In particular, in case of a multi-chip type image sensor, the repetition scanning is necessary for each image sensor chip. Consequently, the blanking time period increases in proportion to the number of the connected image sensor chips and the repetition times of the scanning. As a result, high speed readout of optical signal outputs could not performed sometimes.
Accordingly, the present invention aims to provide a multi-chip type image sensor having a shrunk chip size with desired performance secured.